1. Technical Field
Example embodiments relate a method of forming a metal silicide layer, a semiconductor device including the metal silicide layer, and a method of manufacturing the semiconductor device including the metal silicide layer.
2. Description of the Related Art
The gate width of transistors as well as the thickness and surface area of source/drain regions may be reduced to enhance the integration of semiconductor devices. However, difficulties may arise with regard to reducing the contact and sheet resistance of a gate, a channel, and/or source/drain regions. For example, to reduce contact resistance, a silicide layer may be formed on the gate and the source/drain regions. However, a conventional silicide layer may not have a sufficiently low specific resistance. Additionally, a conventional silicide layer may have agglomeration and diffusion effects which may adversely affect the formation of a relatively uniform and/or thin layer. Consequently, a conventional silicide layer may not provide the lower contact resistance required for next-generation, higher-speed semiconductor devices.